![]() Die Gier nach noch mehr wird im Prinzip nur von einem Faktor beschränkt: Dem Energieverbrauch. Es ist auch nicht abzusehen, dass das Streben nach immer mehr “Flops” demnächst aufhört. Rechenzentren übertreffen sich immer wieder mit noch stärkerer Hardware und noch höheren Geschwindigkeiten ein Problem zu lösen. Parallele Berechnungen auf Hochleistungsrechnern sind heutzutage nicht mehr wegzudenken. To realize the effectiveness of the link usage, brief evaluation of link utilization has been carried out with balanced load. Similarly under synthetic traffic pattern, the proposed FRDS offers an improvement up to 22.51% and 45.53% over DMesh and ZMesh respectively. The experimental results clearly indicates an improvement in power latency product under geometric traffic by 16.27% and 12.23% over DMesh and ZMesh. We adopt constant geometric traffic and the synthetic traffic pattern to measure the performance of proposed FRDS. Further, an average improvement on energy consumption was obtained 8.13% and 5.35% over DMesh and ZMesh. Under normalized condition with respect to Mesh, experimental findings of proposed FRDS against real benchmark traces provide an average improvement on execution time with 1.20% and 4.81% over DMesh and ZMesh. Genetic algorithm (GA) + simulated annealing (SA) have been considered under generic heuristic approach for successful mapping of core into topology and fair comparison of the performance of the proposed FRDS. We propose cluster and generic heuristic based approach For mapping of applications onto FRDS topology. In this paper, we introduce a new hybrid topology namely Four Regular Dense Spidergon (FRDS) based deterministic NoC architecture with 64 cores. NoC futures are allied with intellectual property (IP) reusability, parallel communication within IPs and scalability against standard interconnection NoC topology. Networks-on-Chip (NoC) is an impending research area for designing future System-on-Chip (SoC). The experiments show that these two optimization methods can be adapted to various application scenarios and can further reduce the hardware cost of satellite nodes. In this paper, two optimization directions of the balanced partition routing algorithm are simulated under conditions that the data in the Topo table satisfy μ =5, σ2= 6, σ2=10 and σ2=15, respectively, when comparing their performance indicators. The results reveal that the balanced partition routing algorithm achieves better performance. This paper presents the simulation experiments for the following indexes of the classic inter-satellite routing algorithms and the balanced partition routing algorithm: computation complexity, single-node computation pressure, routing path delay, path delay variance (data in Topo table satisfy μ =5, σ2=10). In this paper, a balanced inter-satellite routing algorithm based on partition routing is proposed. The path delay calculated by the flooding algorithm is small but the calculation is large, while the greedy algorithm is the opposite. However, among the existing inter-satellite routing algorithms, the classical flooding and greedy algorithms and their derivatives also have some limitations. Low-orbit micro-satellite technology has developed rapidly in recent years due to its advantages of low time delay, low cost and short research period.
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